View W49F020_53727.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Preliminary W49F020 256K x 8 CMOS FLASH MEMORY
GENERAL DESCRIPTION
The W49F020 is a 2-megabit, 5-volt only CMOS flash memory organized as 256K x 8 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W49F020 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers.
FEATURES
*
Single 5-volt operations: - 5-volt Read - 5-volt Erase - 5-volt Program
*
Low power consumption - Active current: 25 mA (typ.) - Standby current: 20 A (typ.)
*
Fast Program operation: - Byte-by-Byte programming: 50 S (max.) Fast Erase operation: 100 mS (typ.) Fast Read access time: 70/90 nS Endurance: 1K/10K cycles (typ.) Twenty-year data retention Hardware data protection One 8K byte Boot Block with Lockout protection
* *
Automatic program and erase timing with internal VPP generation End of program or erase detection - Toggle bit - Data polling
* * * * * *
* * * *
Latched address and data TTL compatible I/O JEDEC standard byte-wide pinouts Available packages: 32-pin DIP and 32-pin TSOP and 32-pin-PLCC
-1-
Publication Release Date: October 1999 Revision A1
Preliminary W49F020
PIN CONFIGURATIONS
NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 VDD WE A17 A14 A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3
BLOCK DIAGRAM
W49F020
V DD VSS CE OE WE OUTPUT BUFFER DQ0 . . DQ7
32-pin DIP
26 25 24 23 22 21 20 19 18 17
CONTROL
3FFFF A0 . . A17 MAIM MEMORY 248K BYTES BOOT BLOCK 8K BYTES 02000 01FFF 00000
DECODER
AAA V/ A 1 1 1 N DW 1 2 56 CDE 7 4 3 2 1 32 31 30 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DDGDDDD QQNQQQQ 12D3456 29 28 27 A14 A13 A8 A9 A11 OE A10 CE DQ7
32-pin PLCC
26 25 24 23 22 21
PIN DESCRIPTION
SYMBOL A0-A17 PIN NAME Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground No Connection
A11 A9 A8 A13 A14 A17 WE VDD NC A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3
DQ0-DQ7 CE OE
WE
32-pin TSOP
VDD GND NC
-2-
Preliminary W49F020
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W49F020 is controlled by CE and OE , both of which have to be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed. OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the timing waveforms for further details.
Boot Block Operation
There is an 8K-byte boot block in this device, which can be used to store boot code. The boot block locates in the first 8K bytes of the memory with the address range from 0000(hex) to 1FFF(hex). For the specific code, please see Command Codes for Boot Block Lockout Enable. When the boot block is enabled, data for the designated block cannot be erased or programmed (programming lockout); other memory locations can be changed by the regular programming method. When the boot block programming lockout feature is activated, the chip erase function cannot erase the boot block any longer. In order to detect whether the boot block feature is set on the 8K-bytes block or not, users can perform software command sequence to check it. First, enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address "0002 hex". If the output data is "1," the boot block programming lockout feature is activated; if the output data is "0," the lockout feature is inactivated and the block can be erased/programmed. To return to normal operation, perform a three-byte command sequence (or an alternate single-word command) to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.
Chip Erase Operation
The chip-erase mode can be initiated by a six-word command sequence. After the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed in a fast 100 mS (typical). The host system is not required to provide any control or timing during this operation. If the boot block programming lockout is activated, only the data in the main memory blocks will be erased to FF(hex), and the data in the boot block will not be erased (remains same as before the chip erase operation). The entire memory array will be erased to FF hex by the chip erase operation if the boot block programming lockout feature is not activated. Once the boot block lockout feature is activated, the chip erase function erase the main memory block but not the boot block. The device will automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.
Program Operation
The W49F020 is programmed on a byte-by-byte basis. Program operation can only change logical data "1" to logical data "0." The erase operation (changed entire data in main memory blocks and/or boot block from "0" to "1") is needed before programming. The program operation is initiated by a 4-word command cycle (see Command Codes for Byte Programming). The device will internally enter the program operation immediately after the byte-program command is entered. The internal program timer will automatically time-out (50 S max. -
-3-
Publication Release Date: October 1999 Revision A1
Preliminary W49F020
TBP) when completing programming and return to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle.
Hardware Data Protection
The integrity of the data stored in the W49F020 is also hardware protected in the following ways: (1) Noise/Glitch Protection: A WE pulse with less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than 2.5V typical. (3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 5 mS before any write (erase/program) operation.
Data Polling (DQ7)- Write Status Detection
The W49F020 features a data polling function which used to indicate the end of a program or erase cycle. When the W49F020 is in the internal program or erase cycle, any attemption to read DQ7 of the last word loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and become logical "1" or true data when the erase cycle has been completed.
Toggle Bit (DQ6)- Write Status Detection
In addition to data polling, the W49F020 provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation.
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In software access mode, a three-word (or JEDEC 3-word) command sequence can be used to access the product ID. A read from address 0000H outputs the manufacturer code DA(hex); and a read from address 0001H outputs the device code 8C(hex) for W49F020. The product ID operation can be terminated by a three-word command sequence or an alternated one-word command sequence (see Command Definition table). In the hardware access mode, access to the product ID will be activated by forcing CE and OE low, WE high, and raising A9 to 12 volts.
-4-
Preliminary W49F020
TABLE OF OPERATING MODES
Operating Mode Selection
(VHH = 12V 5%)
MODE Read Write Standby Write Inhibit Output Disable Product ID
CE VIL VIL VIH X X OE VIL VIH X VIL X WE VIH VIL X X VIH
PINS ADDRESS AIN AIN X X X X A0 = VIL; A1-A17 = VIL; A9 = VHH A0 = VIL; A1-A17 = VIL; A9 = VHH Dout Din High Z High Z/DOUT High Z/DOUT
DQ.
X VIL VIL
VIH VIL VIL
X VIH VIH
High Z Manufacturer Code DA (Hex) Device Code 8C (Hex)
TABLE OF COMMAND DEFINITION
COMMAND DESCRIPTION
NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE Cycles Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read Chip Erase Byte Program Boot Block Lockout Product ID Entry Product ID Exit Product ID Exit
Notes:
(1) (1)
1 6 4 6 3 3 1
A IN
DOUT 2AAA 55 2AAA 55 2AAA 55 2AAA 55 2AAA 55 5555 80 5555 A0 5555 80 5555 90 5555 F0 5555 AA AIN D IN 2AAA 55 5555 40 2AAA 55 5555 10
5555 AA 5555 AA 5555 AA 5555 AA 5555 AA XXXX F0
5555 AA
1. Address Format: A14-A0 (Hex); Data Format: DQ7-DQ0 (Hex) 2. Either one of the two Product ID Exit commands can be used.
-5-
Publication Release Date: October 1999 Revision A1
Preliminary W49F020
Command Codes for Byte Program
WORD SEQUENCE 0 Write 1 Write 2 Write 3 Write ADDRESS 5555H 2AAAH 5555H Programmed-Address DATA AAH 55H A0H Programmed-Data
Byte Program Flow Chart
Byte Program Command Flow
Load data AA to address 5555 Load data 55 to address 2AAA Load data A0 to address 5555
Load data Din to programmedaddress
Pause 50 S
Exit
Notes for software program code: Data Format: DQ7-DQ0 (Hex Address Format: A14-A0 (Hex)
-6-
Preliminary W49F020
Command Codes for Chip Erase
BYTE SEQUENCE 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAH 55H 80H AAH 55H 10H
Chip Erase Acquisition Flow
Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555
Pause 1 Sec.
Exit
Notes for chip erase: Data Format: DQ7-DQ0 (Hex) Address Format: A14-A0 (Hex)
-7-
Publication Release Date: October 1999 Revision A1
Preliminary W49F020
Command Codes for Product Identification and Boot Block Lockout Detection
BYTE SEQUENCE ALTERNATE PRODUCT (6) IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION ENTRY ADDRESS 1 Write 2 Write 3 Write 5555 2AAA 5555 Pause 10 S DATA AA 55 90 SOFTWARE PRODUCT IDENTIFICATION/BOOT BLOCK LOCKOUT DETECTION EXIT (7) ADDRESS 5555H 2AAAH 5555H Pause 10 S DATA AAH 55H F0H
Software Product Identification and Boot Block Lockout Detection Acquisition Flow
Product Identification Entry (1)
Load data AA to address 5555
Product Identification and Boot Block Lockout Detection Mode (3)
Product Identification Exit(7)
Load data AA to address 5555 (2)
Load data 55 to address 2AAA
Read address = 00000 data = DA
Load data 55 to address 2AAA
Load data 90 to address 5555
Read address = 00001 data =8C
(2)
Load data F0 to address 5555
Pause 10 S
(4)
Read address = 00002 data in DQ0 = "1"/"0"
Pause 10 S
(5) Normal Mode
Notes for software product identification/boot block lockout detection: (1) Data Format: DQ7-DQ0 (Hex); Address Format: A14-A0 (Hex) (2) A1-A17 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) If the output data in DQ0= " 1," the boot block programming lockout feature is activated; if the output data in DQ0= " 0," the lockout feature is inactivated and the block can be programmed. (5) The device returns to standard operation mode. (6) Optional 1-word cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection.
-8-
Preliminary W49F020
Command Codes for Boot Block Lockout Enable
BYTE SEQUENCE BOOT BLOCK LOCKOUT FEATURE SET ADDRESS 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write 5555H 2AAAH 5555H 5555H 2AAAH 5555H Pause 1 Sec. DATA AAH 55H 80H AAH 55H 40H
Boot Block Lockout Enable Acquisition Flow
Boot Block Lockout Feature Set Flow
Load data AA to address 5555
Load data 55 to address 2AAA
Load data 80 to address 5555
Load data AA to address 5555
Load data 55 to address 2AAA
Load data 40 to address 5555
Pause 1 Sec.
Exit
Notes for boot block lockout enable: Data Format: DQ7-DQ0 (Hex) Address Format: A14-A0 (Hex)
-9-
Publication Release Date: October 1999 Revision A1
Preliminary W49F020
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER Power Supply Voltage to Vss Potential Operating Temperature Storage Temperature D.C. Voltage on Any Pin to Ground Potential except OE Transient Voltage (<20 nS ) on Any Pin to Ground Potential Voltage on OE Pin to Ground Potential RATING -0.5 to +7.0 0 to +70 -65 to +150 -0.5 to VDD +1.0 -1.0 to VDD +1.0 -0.5 to 12.5 UNIT V C C V V V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
DC Operating Characteristics
(VDD = 5.0V 10%, VSS = 0V, TA = 0 to 70 C)
PARAMETER
SYM.
TEST CONDITIONS
LIMITS MIN. TYP. MAX. 50
UNIT
Power Supply Current
ICC
CE = OE = VIL, WE = VIH, all DQs open Address inputs = VIL/VIH, at f = 5 MHz
-
25
mA
Standby VDD Current (TTL input)
ISB1
CE = VIH, all DQs open Other inputs = VIL/VIH CE = VDD -0.3V, all DQs open Other inputs = VDD -0.3V/GND VIN = GND to VDD VOUT = GND to VDD IOL = 2.1 mA
-
2
3
mA
Standby VDD Current ISB2 (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage ILI ILO VIL VIH VOL
-
20
100
A A A V V V V
-0.3 2.0 2.4
-
10 10 0.8 VDD +0.5 0.45 -
VOH IOH = -0.4 mA
- 10 -
Preliminary W49F020
Power-up Timing
PARAMETER Power-up to Read Operation Power-up to Write Operation SYMBOL TPU. READ TPU. WRITE TYPICAL 100 5 UNIT S mS
CAPACITANCE
(VDD = 5.0V, TA = 25 C, f = 1 MHz)
PARAMETER I/O Pin Capacitance Input Capacitance
SYMBOL CI/O CIN
CONDITIONS VI/O = 0V VIN = 0V
MAX. 12 6
UNIT pf pf
AC CHARACTERISTICS
AC Test Conditions
PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load CONDITIONS 0V to 3.0V < 5 nS 1.5V/1.5V 1 TTL Gate and CL = 100 pF for 90nS CL = 30 pF for 70nS
AC Test Load and Waveform
+5V
1.8K
D OUT
30 pF for 70nS 100 pF for 90nS (Including Jig and Scope)
1.3K
Input
3V 1.5V 0V Test Point
Output
1.5V
Test Point
- 11 -
Publication Release Date: October 1999 Revision A1
Preliminary W49F020
AC Characteristics, continued
Read Cycle Timing Parameters
(VCC = 5.0V 10%, VCC = 0V, TA = 0 to 70 C)
PARAMETER
SYM.
W49F020-70 MIN. MAX. 70 70 35 25 25 -
W49F020-90 MIN. 90 0 0 0 MAX. 90 90 40 25 25 -
UNIT
Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time
CE Low to Active Output OE Low to Active Output CE High to High-Z Output OE High to High-Z Output
TRC TCE TAA TOE TCLZ TOLZ TCHZ TOHZ TOH
70 0 0 0
nS nS nS nS nS nS nS nS nS
Output Hold from Address Change
Write Cycle Timing Parameters
PARAMETER Address Setup Time Address Hold Time WE and CE Setup Time WE and CE Hold Time OE High Setup Time OE High Hold Time
CE Pulse Width
SYMBOL TAS TAH TCS TCH TOES TOEH TCP TWP TWPH TDS TDH TBP TEC
MIN. 0 50 0 0 0 0 100 100 100 50 0 -
TYP. 10 0.1
MAX. 50 1
UNIT nS nS nS nS nS nS nS nS nS nS nS S S
WE Pulse Width WE High Width Data Setup Time Data Hold Time Byte programming Time Erase Cycle Time
Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.
- 12 -
Preliminary W49F020
AC Characteristics, continued
Data Polling and Toggle Bit Timing Parameters
PARAMETER SYM. W49F020-70 MIN. OE to Data Polling Output Delay
CE to Data Polling Output Delay
W49F020-90 MIN. MAX. 40 90 40 90
UNIT
MAX. 35 70 35 70
TOEP TCEP TOET TCET
-
nS nS nS nS
OE to Toggle Bit Output Delay CE to Toggle Bit Output Delay
TIMING WAVEFORMS
Read Cycle Timing Diagram
TRC Address A17-0 CE TCE
OE
TOE
WE
VIH
TOLZ
T OHZ
TCLZ High-Z DQ7-0
TOH Data Valid TAA
TCHZ High-Z Data Valid
- 13 -
Publication Release Date: October 1999 Revision A1
Preliminary W49F020
Timing Waveforms, continued
WE Controlled Command Write Cycle Timing Diagram
TAS Address A17-0
TAH
CE
TCS TOES
TCH T OEH
OE TWP TWPH
WE
TDS DQ7-0 Data Valid
TDH
CE Controlled Command Write Cycle Timing Diagram
TAS
TAH
Address A17-0 TCPH TCP CE TOES OE TOEH
WE TDS DQ7-0 High Z Data Valid
TDH
- 14 -
Preliminary W49F020
Timing Waveforms, continued
Program Cycle Timing Diagram
Byte Program Cycle Address A17-0 5555 2AAA 5555 Address
DQ7-0
AA
55
A0
Data-In
CE
OE TWP WE Byte 0
T WPH
TBP
Byte 1
Byte 2
Byte 3
Internal Write Start
DATA Polling Timing Diagram
Address A17-0 WE TCEP CE TOEH OE TOEP DQ7 X X TBP or TEC X X TOES
- 15 -
Publication Release Date: October 1999 Revision A1
Preliminary W49F020
Timing Waveforms, continued
Toggle Bit Timing Diagram
Address A17-0
WE
CE TOEH OE TOES
DQ6 TBP orTEC
Boot Block Lockout Enable Timing Diagram
Six byte code for Boot Block Lockout Feature Enable Address A17-0 5555 2AAA 5555 5555 2AAA 5555
DQ7-0 CE
XXAA
XX55
XX80
XXAA
XX55
XX40
OE WE
TWP TWPH SB0 SB1 SB2 SB3 SB4 SB5
TEC
- 16 -
Preliminary W49F020
Timing Waveforms, continued
Chip Erase Timing Diagram
Six-byte code for 5V-only software chip erase Address A17-0 5555 2AAA 5555 5555 2AAA 5555
DQ7-0
XXAA
XX55
XX80
XXAA
XX55
XX10
CE
OE WE
TWP TWPH SB0 SB1 SB2 SB3 SB4 SB5
TEC
Internal Erase starts
- 17 -
Publication Release Date: October 1999 Revision A1
Preliminary W49F020
ORDERING INFORMATION
PART NO. ACCESS TIME (nS) POWER SUPPLY CURRENT MAX. (mA) W49F020-70 W49F020-90 W29F020Q-70 W29F020Q-90 W29F020P-70 W29F020P-90 W49F020-70B W49F020-90B W29F020Q-70B W29F020Q-90B W29F020P-70B W29F020P-90B
Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 3. There are two kinds of boot block in this device. The part number shown in the Ordering Information table is only for Bottom Boot Block part, which is in the lower address range. For the requirement of the higher address range boot block, the Top Boot Block, please contact Winbond FAE for details.
STANDBY VDD CURRENT MAX. (A) 100 (CMOS) 32-pin DIP 100 (CMOS) 32-pin DIP
PACKAGE
CYCLE
70 90 70 90 70 90 70 90 70 90 70 90
50 50 50 50 50 50 50 50 50 50 50 50
1K 1K 1K 1K 1K 1K 10K 10K 10K 10K 10K 10K
100 (CMOS) 32-pin TSOP (8 mm x 20 mm) 100 (CMOS) 32-pin TSOP (8 mm x 20 mm) 100 (CMOS) 32-pin PLCC 100 (CMOS) 32-pin PLCC 100 (CMOS) 32-pin DIP 100 (CMOS) 32-pin DIP 100 (CMOS) 32-pin TSOP (8 mm x 20 mm) 100 (CMOS) 32-pin TSOP (8 mm x 20 mm) 100 (CMOS) 32-pin PLCC 100 (CMOS) 32-pin PLCC
- 18 -
Preliminary W49F020
PACKAGE DIMENSIONS
32-pin P-DIP
Dimension in inches
Dimension in mm
Symbol
Min. Nom. Max.
0.210 0.010 0.150 0.016 0.048 0.155 0.018 0.050 0.160 0.022 0.054 0.014 1.660 0.610 0.555 0.110 0.140 15
Min. Nom. Max.
5.33 0.25 3.81 0.41 1.22 0.20 3.94 0.46 1.27 0.25 4.06 0.56 1.37 0.36
D
32 17
E1
A A1 A2 B B1 c D E E1 e1 L
a
0.008 0.010 1.650 0.590 0.545 0.090 0.120 0 0.630 0.650 0.600 0.550 0.100 0.130
41.91 42.16 14.99 15.24 13.84 2.29 3.05 0 16.51 15.49
13.97 14.10 2.54 3.30 2.79 3.56 15 17.02 2.16
1
16
eA S Notes:
E c
0.670 16.00 0.085
S
A A2 L B B1
A1
Base Plane Seating Plane
e1
a
eA
1.Dimensions D Max. & S include mold flash or tie bar burrs. 2.Dimension E1 does not include interlead flash. 3.Dimensions D & E1. include mold mismatch and are determined at the mold parting line. 4.Dimension B1 does not include dambar protrusion/intrusion. 5.Controlling dimension: Inches 6.General appearance spec. should be based on final visual inspection spec.
32-pin PLCC
Symbol
HE E 4 1 32 30
Dimension in Inches
Dimension in mm
Min.
0.020 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075
Nom.
Max.
0.140
Min.
0.50
Nom.
Max.
3.56
5
29
GD D HD
A A1 A2 b1 b c D E e GD GE HD HE L y Notes:
0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.51 0 0.410 0.590 0.49 0 0.090
0.115 0.032 0.022 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.004
2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91
2.80 0.71 0.46 0.25 13.97 11.43 1.27 12.9 5 10.41 14.99 12.45 2.29
2.93 0.81 0.56 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.10
0
10
0
10
13
21
14
20
c
L A2 A
1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection sepc.
Seating Plane
e
b b1 GE
A1 y
- 19 -
Publication Release Date: October 1999 Revision A1
Preliminary W49F020
Package Dimensions, continued
32-pin TSOP
HD
Symbol
Dimension in Inches Min. Nom. Max.
0.047 0.002 0.037 0.007 0.005 0.720 0.311 0.780
Dimension in mm Min. Nom. Max.
1.20 0.15 1.05 0.23 0.17 18.50 8.10 20.20
D c
A A1 A2
__
__ __
0.039 0.008 0.006 0.724 0.315 0.787 0.020 0.020 0.031 0.006 0.041 0.009 0.007 0.728 0.319 0.795
__
0.05 0.95 0.17 0.12 18.30 7.90 19.80
__ __
1.00 0.20 0.15 18.40 8.00 20.00 0.50 0.50 0.80
M
e E
b c D
0.10(0.004)
b
E HD e L L
A A2 L L1 A1
1
__
0.016
__
0.024
__
0.40
__
0.60
__
0.000 1
__
0.004 5
__
0.00 1
__
0.10 5
Y
__
3
__
3
Y
Note:
Controlling dimension: Millimeters
- 20 -
Preliminary W49F020
VERSION HISTORY
VERSION A1 DATE Oct. 1999 PAGE Initial Issued DESCRIPTION
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
- 21 -
Publication Release Date: October 1999 Revision A1

▲Up To Search▲

Price & Availability of W49F020

	To Download W49F020 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .